The present invention relates to electrical switch circuits and, more particularly, to methods and devices for decreasing the turn-on time in electrical switches that include one or more conductivity modulated field effect transistors (COMFETs) through the innovative use of metal oxide semiconductor field effect transistors (MOSFETs).
With reference to FIG. 1, MOSFETs are voltage driven devices 10 with a gate G that is electrically isolated from the device's silicon body 12 by a thin layer of silicon dioxide (SiO.sub.2) 14. MOSFETs are majority carrier semiconductors that operate at much higher speeds than bipolar transistors because there is no charge-storage mechanism. A positive voltage applied to the gate G of an N type MOSFET creates an electric field in the channel region 16 beneath the gate G; that is, the electric charge on the gate causes the portion of the P type body region 18 beneath the gate to convert to an N region. This conversion allows current to flow between the drain D and source S metals through an N type drain material as indicated by the dotted arrows in the figure. In effect, the MOSFET ceases to be an N-P-N device when in this state. A useful by-product of the MOSFET process is the internal parasitic diode formed between source 17 and drain 13 that is useful as a clamp diode in inductive-load switching.
With reference now to FIG. 2, COMFETs are similar in structure to MOSFETs, but the conductivity of the N type epitaxial voltage blocking layer 20 is greatly increased (modulated) by the injection of minority carriers from a P type anode 22. A COMFET is a four layer (N-P-N-P) device with a MOS-gated channel 34 connecting the two N-type regions. In the normal mode of operation, a positive voltage is applied to the drain relative to the source. When the gate is at zero potential with respect to the source, no anode current flows when the anode voltage V.sub.A is below the breakdown level V.sub.BF. When V.sub.A &lt;V.sub.BF and the gate voltage is larger than the threshold voltage value V.sub.gt, electrons pass into the N.sup.- drain region 20 (the base of the P-N-P transistor). These electrons lower the potential of the N.sup.- drain region 20, forward biasing the P.sup.+ N.sup.- junction, thereby causing holes to be injected from the P.sup.+ anode 22 into the N.sup.- drain region 20. The excess electrons and holes modulate the conductivity of the high resistivity N.sup.- drain region, dramatically reducing the on-resistance of the device.
Since a COMFET is a four layer structure, it could latch on. That is, the device would remain conductive and the gate would be unable to control it if the sum of the alphas of the integral NPN and PNP transistors were to exceed unity. This is prevented by the shunting resistance R.sub.s formed by the source metal 24 shorting the N+ source region 26 and the P+ well body region 28. During normal operation, the shunting resistance R.sub.S keeps the emitter current of the N-P-N transistor very low, which keeps .alpha..sub.NPN very low. COMFETs are also known as insulated gate rectifiers (IGRs), gain enhanced field effect transistors (GEMFETs) and insulated gate transistors (IGTs). See, for example, U.S. Pat. No. 4,364,073 issued Dec. 14, 1982 to Becke, et al.
A COMFET structure may be modified to increase the latching current I.sub.L (the level of anode current when .alpha..sub.NPN +.alpha..sub.PNP increases to 1 causing the device to latch) by the addition of a thin (about 10 microns) layer 30 (a punchthrough barrier) of N.sup.+ silicon in the epitaxial structure between the N- drain region 20 and the P.sup.+ anode region 22. This layer 30 lowers the emitter injection efficiency of the P-N-P transistor equivalent circuit and results in an increase of I.sub.L by a factor of 2 to 3. In addition, there is a reduction in fall time t.sub.f.
A plot of anode-to-source current I.sub.AS versus voltage V.sub.AS for various gate voltages V.sub.G in a typical COMFET is shown in FIG. 3 and the anode-to-source current I.sub.AS versus voltage V.sub.AS for gate voltages V.sub.G in a typical MOSFET is illustrated in FIG. 4. By comparing these two figures, it may be seen that, for a given gate voltage V.sub.G and a given anode-to-source voltage V.sub.AS above approximately one volt, the COMFET can carry more current than the MOSFET, Below about one volt V.sub.AS the COMFET current drops rapidly to almost zero, while the MOSFET current continues down an essentially ohmic trace. When anode-to-source voltage V.sub.AS goes negative, the COMFET carries almost no current while the MOSFET continues down along the same ohmic trace it had in the positive voltage. At about one negative volt V.sub.AS, the resistance in the MOSFET drops off rapidly as current begins to flow across the forward direction of body-drain region junction 32. Thus, the MOSFET minimizes the discontinuity in voltage drop as the current through the device goes from forward to reverse, while the COMFET has the ability to carry a larger current for a given gate voltage V.sub.G and anode-to-source voltage V.sub.AS (above one volt).
Accordingly, it is an object of the present invention to provide a novel method and device to use a MOSFET to improve the performance of a COMFET-based electrical switch.
It is a further object of the present invention to provide a novel semiconductor switch circuit having a COMFET and MOSFET connected substantially in parallel.
It is yet a further object of the present invention to provide a novel semiconductor device in which a COMFET and MOSFET are connected substantially in parallel in a single semiconductor chip.
It is another object of the present invention to provide a novel method of decreasing the turn-off time of a COMFET by shorting the COMFET lower emitter region to remove stored charge.
It is yet another object of the present invention to provide a novel method of increasing the latch-up current of a COMFET semiconductor switch by locating a MOSFET drain region remote from the gate metal contacts of the COMFET.
These and many other objects and advantages will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.